Invention Grant
US08176460B2 Method of optimizing ESD protection for an IC, an ESD protection optimizer and an ESD protection optimization system
有权
优化IC的ESD保护方法,ESD保护优化器和ESD保护优化系统
- Patent Title: Method of optimizing ESD protection for an IC, an ESD protection optimizer and an ESD protection optimization system
- Patent Title (中): 优化IC的ESD保护方法,ESD保护优化器和ESD保护优化系统
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Application No.: US12434578Application Date: 2009-05-01
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Publication No.: US08176460B2Publication Date: 2012-05-08
- Inventor: Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
- Applicant: Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Alan A. R. Cooper; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.
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