Invention Grant
- Patent Title: Interfacial barrier for work function modification of high performance CMOS devices
- Patent Title (中): 高性能CMOS器件功能修改界面屏障
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Application No.: US12488569Application Date: 2009-06-21
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Publication No.: US08178939B2Publication Date: 2012-05-15
- Inventor: Wei-Yip Loh , Prashant Majhi , Brian Coss
- Applicant: Wei-Yip Loh , Prashant Majhi , Brian Coss
- Applicant Address: US TX Austin
- Assignee: Sematech, Inc.
- Current Assignee: Sematech, Inc.
- Current Assignee Address: US TX Austin
- Agency: Fulbright & Jaworski L.L.P.
- Main IPC: H01L29/47
- IPC: H01L29/47 ; H01L29/788 ; H01L29/94 ; H01L29/76 ; H01L29/78

Abstract:
A semiconductor structure may include a semiconductor bulk region with a gate stack on the semiconductor bulk region. The source region and the drain region in the semiconductor bulk region may be located on opposing sides of a channel region below the gate stack. An interfacial layer coupled to the channel region may modify a workfunction of a metal-semiconductor contact. In a MOSFET, the metal-semiconductor contact may be between a metal contact and the source region and the drain region. In a Schottky barrier-MOSFET, the metal-semiconductor contact may be between a silicide region in the source region and/or the drain region and the channel region. The interfacial layer may use a dielectric-dipole mitigated scheme and may include a conducting layer and a dielectric layer. The dielectric layer may include lanthanum oxide or aluminum oxide used to tune the workfunction of the metal-semiconductor contact.
Public/Granted literature
- US20100320510A1 Interfacial Barrier for Work Function Modification of High Performance CMOS Devices Public/Granted day:2010-12-23
Information query
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