Invention Grant
- Patent Title: Method of forming high-k dual dielectric stack
- Patent Title (中): 形成高k双电介质叠层的方法
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Application No.: US12229624Application Date: 2008-08-26
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Publication No.: US08178952B2Publication Date: 2012-05-15
- Inventor: Jun-Fei Zheng , George Chen , Wilman Tsai
- Applicant: Jun-Fei Zheng , George Chen , Wilman Tsai
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/58
- IPC: H01L23/58
Abstract:
The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer.
Public/Granted literature
- US20090004882A1 Method of forming high-k dual dielectric stack Public/Granted day:2009-01-01
Information query
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