Invention Grant
- Patent Title: Digitally calibrated high speed clock distribution
- Patent Title (中): 数字校准的高速时钟分配
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Application No.: US12723285Application Date: 2010-03-12
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Publication No.: US08179173B2Publication Date: 2012-05-15
- Inventor: Erick M. Hirata , Lloyd F. Linder
- Applicant: Erick M. Hirata , Lloyd F. Linder
- Applicant Address: US MA Waltham
- Assignee: Raytheon Company
- Current Assignee: Raytheon Company
- Current Assignee Address: US MA Waltham
- Agency: Christie, Parker & Hale, LLP
- Main IPC: H03L7/00
- IPC: H03L7/00 ; H03H11/16

Abstract:
An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; loop filters for generating and transmitting respective DC voltage feedback signals; current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.
Public/Granted literature
- US20110221486A1 DIGITALLY CALIBRATED HIGH SPEED CLOCK DISTRIBUTION Public/Granted day:2011-09-15
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