A signal processor comprises a reference voltage circuit (RVC) for imposing a reference voltage (VR) onto a capacitance (Cr). The reference voltage circuit (RVC) comprises a negative slope module (NSM) for providing a negative slope signal (SN), which has a magnitude that decreases when a voltage that is present on the capacitance (Cr) increases. A positive slope module (PSM) provides a positive slope signal (SP), which has a magnitude that increases when the voltage that is present on the capacitance (Cr) increases. A minimum selection module (MSM) controls a maximum current (IMX) that the reference voltage circuit (RVC) can apply to the capacitance (Cr) substantially in dependence on the negative slope signal (SN), if the magnitude of the negative slope signal (SN) is smaller than that of the positive slope signal (SP). The minimum selection module (MSM) controls the maximum current substantially in dependence on the positive slope signal (SP), if the magnitude of the positive slope signal (SP) is smaller than that of the negative slope signal (SN).