Invention Grant
US08180011B2 Clock and data recovery loop with ISI pattern-weighted early-late phase detection
有权
具有ISI模式加权早期相位检测的时钟和数据恢复回路
- Patent Title: Clock and data recovery loop with ISI pattern-weighted early-late phase detection
- Patent Title (中): 具有ISI模式加权早期相位检测的时钟和数据恢复回路
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Application No.: US12507034Application Date: 2009-07-21
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Publication No.: US08180011B2Publication Date: 2012-05-15
- Inventor: Viet Linh Do , Wei Fu
- Applicant: Viet Linh Do , Wei Fu
- Applicant Address: US CA San Diego
- Assignee: Applied Micro Circuits Corporation
- Current Assignee: Applied Micro Circuits Corporation
- Current Assignee Address: US CA San Diego
- Agency: Law Office of Gerald Maliszewski
- Agent Gerald Maliszewski
- Main IPC: H04L7/00
- IPC: H04L7/00 ; H04L25/00 ; H04L25/40

Abstract:
An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated, where the Q clock has a fixed phase delay with respect to the I clock. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I and Q clocks, creating digital I-bit and Q-bit values, respectively. The I-bit values and Q-bit values are segmented into n-bit digital words. In response to analyzing the I-bit and Q-bit values, I clock phase corrections are identified. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. A phase error signal is generated by averaging the weighted I-bit values for each n-bit digital word, and I clock is modified in phase.
Public/Granted literature
- US20090279653A1 Clock and Data Recovery Loop with ISI Pattern-Weighted Early-Late Phase Detection Public/Granted day:2009-11-12
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