Invention Grant
- Patent Title: Test fail analysis on VLSI chips
- Patent Title (中): VLSI芯片测试故障分析
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Application No.: US12326166Application Date: 2008-12-02
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Publication No.: US08180142B2Publication Date: 2012-05-15
- Inventor: Martin Eckert , Georg Goecke , Marta Junginger , Klaus Kempter , Markus Ulbricht
- Applicant: Martin Eckert , Georg Goecke , Marta Junginger , Klaus Kempter , Markus Ulbricht
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Libby Toub
- Main IPC: G06K9/03
- IPC: G06K9/03

Abstract:
Compact graphical representations of common test fail signatures and process related test fails are provided through methods of selecting, calculating and/or presenting information. The input may be a list of failing tests on a sample of devices under test from chip and/or wafer process fails. The failing tests are identified and then other tests that fail at the same time may be identified. Several graphical outputs are provided, including all possible combinations between test fails and between test fails and process fails. The dependencies are printed as sorted two dimensional bitmaps that are compact representations of the results using color codes. Subtraction of two independent bitmaps is provided, which eliminates common properties and emphasizes differences between multiple bitmaps which allows for quick identification of differences of process fails potentially different between the two different bitmaps indicating potential root causes for the selected one of the test fails.
Public/Granted literature
- US20100135570A1 TEST FAIL ANALYSIS ON VLSI CHIPS Public/Granted day:2010-06-03
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