Invention Grant
US08180228B1 Programmable phase detector for sequence equalizer for optical channels
有权
用于光通道的序列均衡器的可编程相位检测器
- Patent Title: Programmable phase detector for sequence equalizer for optical channels
- Patent Title (中): 用于光通道的序列均衡器的可编程相位检测器
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Application No.: US12273597Application Date: 2008-11-19
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Publication No.: US08180228B1Publication Date: 2012-05-15
- Inventor: James Harley , Chuandong Li
- Applicant: James Harley , Chuandong Li
- Applicant Address: US MD Linthicum
- Assignee: Ciena Corporation
- Current Assignee: Ciena Corporation
- Current Assignee Address: US MD Linthicum
- Agency: Blake, Cassels & Graydon LLP
- Agent Kent Daniels
- Main IPC: H04B10/06
- IPC: H04B10/06

Abstract:
In a direct-detection receiver having an analog-to-digital converter (ADC) for sampling a received optical signal and a sequence estimator for recovering data symbols from a multi-bit sample stream generated by the ADC, a method of acquiring a channel lock condition of a clock recovery block of the receiver. A plurality of sets of channel statistics are provided. Each set of channel statistics optimizes performance of the sequence estimator for a respective predetermined combination of channel chromatic dispersion and polarization mode dispersion. At least one set of channel statistics will, when installed in the sequence estimator, yield symbol estimates having residual distortions that are within an acquisition range of the clock recovery block. During start-up of the receiver, one of the sets of channel statistics is selected and installed in the Sequence Estimator. If a channel lock condition is not detected within a predetermined time interval, the step of selecting one of the sets of channel statistics and installing the selected set of channel statistics in the Sequence Estimator is repeated until a channel lock condition is detected.
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