Invention Grant
US08180975B2 Controlling interference in shared memory systems using parallelism-aware batch scheduling
有权
使用并行感知批处理调度来控制共享存储器系统中的干扰
- Patent Title: Controlling interference in shared memory systems using parallelism-aware batch scheduling
- Patent Title (中): 使用并行感知批处理调度来控制共享存储器系统中的干扰
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Application No.: US12037102Application Date: 2008-02-26
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Publication No.: US08180975B2Publication Date: 2012-05-15
- Inventor: Thomas Moscibroda , Onur Mutlu
- Applicant: Thomas Moscibroda , Onur Mutlu
- Applicant Address: US WA Redmond
- Assignee: Microsoft Corporation
- Current Assignee: Microsoft Corporation
- Current Assignee Address: US WA Redmond
- Agency: Lyon & Harr, LLP
- Agent Mark A. Watson
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F9/46

Abstract:
A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism. Further, rank-based request scheduling may be performed with or without batching.
Public/Granted literature
- US20090217273A1 CONTROLLING INTERFERENCE IN SHARED MEMORY SYSTEMS USING PARALLELISM-AWARE BATCH SCHEDULING Public/Granted day:2009-08-27
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