Invention Grant
US08180998B1 System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations
有权
处理单元的通道系统通过用于数据并行或任务并行操作的共享存储器单元接收指令
- Patent Title: System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations
- Patent Title (中): 处理单元的通道系统通过用于数据并行或任务并行操作的共享存储器单元接收指令
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Application No.: US12208231Application Date: 2008-09-10
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Publication No.: US08180998B1Publication Date: 2012-05-15
- Inventor: Monier Maher , Christopher Lamb , Sanjay J. Patel , Peter Hsu
- Applicant: Monier Maher , Christopher Lamb , Sanjay J. Patel , Peter Hsu
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan, LLP
- Main IPC: G06F15/16
- IPC: G06F15/16
Abstract:
A system for performing data-parallel operations and task-parallel operations. A first switch fabric node (SFN) includes first and second lane processing engines (LPEs). The first LPE includes a first set of lane processing units (LPUs) configured to perform data-parallel operations, where each LPU performs a set of operations, and each LPU uses a different set of data for the set of operations, and each LPU within the first set of LPUs uses a different set of data for the set of operations. The second LPE includes a second set of LPUs configured to perform task-parallel operations, where each LPU performs a different set of operations. A processing control engine (PCE) is configured to distribute instructions and data to the first LPE and the second LPE. Advantageously, data parallel operations and task parallel operations are able to be performed on the same processor simultaneously.
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