Invention Grant
- Patent Title: Combinational equivalence checking for threshold logic circuits
- Patent Title (中): 阈值逻辑电路的组合等价检验
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Application No.: US12401982Application Date: 2009-03-11
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Publication No.: US08181133B2Publication Date: 2012-05-15
- Inventor: Tejaswi Gowda , Sarma Vrudhula
- Applicant: Tejaswi Gowda , Sarma Vrudhula
- Applicant Address: US AZ Scottsdale
- Assignee: Arizona Board of Regents for and on behalf of Arizona State University
- Current Assignee: Arizona Board of Regents for and on behalf of Arizona State University
- Current Assignee Address: US AZ Scottsdale
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate.
Public/Granted literature
- US20090235216A1 Combinational Equivalence Checking for Threshold Logic Circuits Public/Granted day:2009-09-17
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