A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit.