An arbitrator circuit for accessing a bus comprises a logic gate arrangement (406), one input of which is coupled to a first bus line. The circuit comprises a switching arrangement (404, 405, 407). As a response to a control signal the switching arrangement disconnects a first half (402) of the first bus line from a second half (403), and couples the second half (403) to a first fixed potential. A second bus line (401) is decoupled from the logic gate arrangement (406), which is coupled to receive a second fixed potential. The second bus line is coupled to the first fixed potential. Two sources are available for providing the control signal to the switching arrangement (404, 405, 407). One of them is the output of the logic gate arrangement (406).