Invention Grant
US08190809B2 Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
有权
分流交织用于访问多个存储体，特别是具有部分访问的包含高速缓存行数据的单元的单元
- Patent Title: Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
- Patent Title (中): 分流交织用于访问多个存储体，特别是具有部分访问的包含高速缓存行数据的单元的单元
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Application No.: US12698719Application Date: 2010-02-02
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Publication No.: US08190809B2Publication Date: 2012-05-29
- Inventor: Maurice L. Hutson
- Applicant: Maurice L. Hutson
- Applicant Address: US MN Rochester
- Assignee: Efficient Memory Technology
- Current Assignee: Efficient Memory Technology
- Current Assignee Address: US MN Rochester
- Agency: Westerman, Champlin & Kelly, P.A.
- Main IPC: G06F12/06
- IPC: G06F12/06
Abstract:
A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage location. Each storage location contains a respective bank select. The addressable locations and storage locations are grouped into interleave patterns such that, for each pattern, there are Q storage locations and 2A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and a remainder loop containing R sequentially addressable locations, where L·Q+R=2A. A shunt defines a non-zero offset for each interleave so that each interleave commences with a different bank select and a complete rotation of all of the interleaves addresses each of the memory banks an equal number of times. The shunt (S) may be selected as mod(2A,Q), −Q+mod(2A,Q), ±1 or ±prime to , where −
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