Invention Grant
- Patent Title: Critical section detection and prediction mechanism for hardware lock elision
- Patent Title (中): 硬件锁定检测的关键部分检测和预测机制
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Application No.: US11599009Application Date: 2006-11-13
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Publication No.: US08190859B2Publication Date: 2012-05-29
- Inventor: Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
- Applicant: Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent David P. McAbee
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.
Public/Granted literature
- US20080115042A1 Critical section detection and prediction mechanism for hardware lock elision Public/Granted day:2008-05-15
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