Invention Grant
US08190944B2 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed
有权
配置为以不同时钟速度运行的多个链路的时钟速度切换的设备和切换时钟速度的方法
- Patent Title: Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed
- Patent Title (中): 配置为以不同时钟速度运行的多个链路的时钟速度切换的设备和切换时钟速度的方法
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Application No.: US12635942Application Date: 2009-12-11
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Publication No.: US08190944B2Publication Date: 2012-05-29
- Inventor: Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
- Applicant: Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
- Applicant Address: CA Markham, Ontario
- Assignee: ATI Technologies ULC
- Current Assignee: ATI Technologies ULC
- Current Assignee Address: CA Markham, Ontario
- Agency: Volpe And Koenig, P.C.
- Main IPC: G06F12/06
- IPC: G06F12/06 ; H04B10/24

Abstract:
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.
Public/Granted literature
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