Invention Grant
US08191026B2 Semiconductor integrated circuit and switch arranging and wiring method
有权
半导体集成电路和开关布置及布线方法
- Patent Title: Semiconductor integrated circuit and switch arranging and wiring method
- Patent Title (中): 半导体集成电路和开关布置及布线方法
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Application No.: US12314111Application Date: 2008-12-04
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Publication No.: US08191026B2Publication Date: 2012-05-29
- Inventor: Tetsuo Motomura
- Applicant: Tetsuo Motomura
- Applicant Address: JP Tokyo
- Assignee: Sony Corporation
- Current Assignee: Sony Corporation
- Current Assignee Address: JP Tokyo
- Agency: Rader Fishman & Grauer, PLLC
- Priority: JP2008-008197 20080117
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A semiconductor integrated circuit includes: a circuit block having a first power supply line to which one of a power supply voltage and a reference voltage is applied, an internal voltage line, and a circuit cell connected between the first power supply line and the internal voltage line; and a plurality of switch cells each including two voltage cell lines each connected electrically to the internal voltage line, two power cell lines each connected electrically to a second power supply line to which another of the power supply voltage and the reference voltage is applied, a control cell line electrically connected to a switch control line, and a transistor electrically connected between the internal voltage line and the second power supply line.
Public/Granted literature
- US20090184758A1 Semiconductor integrated circuit and switch arranging and wiring method apparatus Public/Granted day:2009-07-23
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