Invention Grant
US08191030B2 Identifying parasitic diode(s) in an integrated circuit physical design
有权
识别集成电路物理设计中的寄生二极管
- Patent Title: Identifying parasitic diode(s) in an integrated circuit physical design
- Patent Title (中): 识别集成电路物理设计中的寄生二极管
-
Application No.: US12337061Application Date: 2008-12-17
-
Publication No.: US08191030B2Publication Date: 2012-05-29
- Inventor: Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
- Applicant: Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Richard Kotulak
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455
Abstract:
A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
Public/Granted literature
- US20090150842A1 IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN Public/Granted day:2009-06-11
Information query
