Invention Grant
- Patent Title: Monolithic semiconductor switches and method for manufacturing
- Patent Title (中): 单片半导体开关及其制造方法
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Application No.: US13081642Application Date: 2011-04-07
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Publication No.: US08193559B2Publication Date: 2012-06-05
- Inventor: Oliver Haeberlen , Walter Rieger , Martin Vielemeyer , Lutz Goergens , Martin Poelzl , Milko Paolucci , Johannes Schoiswohl , Joachim Krumrey
- Applicant: Oliver Haeberlen , Walter Rieger , Martin Vielemeyer , Lutz Goergens , Martin Poelzl , Milko Paolucci , Johannes Schoiswohl , Joachim Krumrey , Sonja Krumrey, legal representative
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.
Public/Granted literature
- US20110241170A1 MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING Public/Granted day:2011-10-06
Information query
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