Invention Grant
US08193583B2 Monolithic output stage with vertical high-side PMOS and vertical low-side NMOS interconnected using buried metal, structure and method
失效
具有垂直高边PMOS和垂直低端NMOS的单片输出级使用埋入金属互连,结构和方法
- Patent Title: Monolithic output stage with vertical high-side PMOS and vertical low-side NMOS interconnected using buried metal, structure and method
- Patent Title (中): 具有垂直高边PMOS和垂直低端NMOS的单片输出级使用埋入金属互连,结构和方法
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Application No.: US12717976Application Date: 2010-03-05
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Publication No.: US08193583B2Publication Date: 2012-06-05
- Inventor: François Hébert
- Applicant: François Hébert
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas, Inc.
- Current Assignee: Intersil Americas, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Fogg & Powers LLC
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H01L21/336

Abstract:
A voltage converter can include an output circuit having a vertical high-side device and a vertical low-side device which can be formed on a single die (i.e. a “PowerDie”). The high side device can be a PMOS transistor, while the low side device can be an NMOS transistor. The source of the PMOS transistor and the source of the NMOS transistor can be formed from the same metal structure, with the source of the high side device electrically connected to VIN and the source of the low side device electrically connected to ground. A drain of the high side PMOS transistor can be electrically shorted to the drain of the low side NMOS transistor during device operation using a metal layer which is interposed between the transistors and a semiconductor substrate.
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