Invention Grant
- Patent Title: Interconnecting bit lines in memory devices for multiplexing
- Patent Title (中): 存储器件中的位线互连用于复用
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Application No.: US13154559Application Date: 2011-06-07
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Publication No.: US08193590B2Publication Date: 2012-06-05
- Inventor: Seiichi Aritome
- Applicant: Seiichi Aritome
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: H01L29/76
- IPC: H01L29/76
Abstract:
An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs.
Public/Granted literature
- US20110233686A1 INTERCONNECTING BIT LINES IN MEMORY DEVICES FOR MULTIPLEXING Public/Granted day:2011-09-29
Information query
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