Invention Grant
- Patent Title: Semiconductor die package with clip interconnection
- Patent Title (中): 半导体管芯封装带夹子互连
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Application No.: US12334249Application Date: 2008-12-12
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Publication No.: US08193618B2Publication Date: 2012-06-05
- Inventor: Ruben P. Madrid
- Applicant: Ruben P. Madrid
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/60

Abstract:
A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first lead structure comprising a die attach pad, a second lead structure, and a third lead structure. It also includes a semiconductor die comprising a first surface and a second surface. The semiconductor die is on the die attach pad of the leadframe structure. The first surface is proximate the die attach pad. The semiconductor die package further includes a clip structure comprising a first interconnect structure and a second interconnect structure, the first interconnect structure comprising a planar portion and a protruding portion, the protruding portion including an exterior surface and side surfaces defining the exterior surface. The protruding portion extends from the planar portion of the first interconnect structure. The second surface of the semiconductor die is proximate to the clip structure, and a molding material covers at least the semiconductor die and at least a portion of the side surfaces of the protruding portion.
Public/Granted literature
- US20100148327A1 SEMICONDUCTOR DIE PACKAGE WITH CLIP INTERCONNECTION Public/Granted day:2010-06-17
Information query
IPC分类: