Invention Grant
- Patent Title: Stacked-chip packaging structure and fabrication method thereof
- Patent Title (中): 堆叠芯片封装结构及其制造方法
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Application No.: US12583725Application Date: 2009-08-24
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Publication No.: US08193625B2Publication Date: 2012-06-05
- Inventor: Chun-Kai Liu , Chih-Kuang Yu , Ming-Ji Dai , Ming-Che Hsieh
- Applicant: Chun-Kai Liu , Chih-Kuang Yu , Ming-Ji Dai , Ming-Che Hsieh
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: J.C. Patents
- Priority: TW98116156A 20090515
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A stacked-chip packaging structure includes chip sets, a heat sink, a substrate, a circuit board, and solder balls. The chip sets are stacked together, each of which has a heat-dissipation structure and a chip. The heat-dissipation structure has a chip recess, through holes arranged in the chip recess, and an extending portion extending from the chip recess. The chip disposed in the chip recess has bumps. Each bump on the chip is correspondingly disposed in one of the through holes of the heat-dissipation structure. The extending portion of the heat-dissipation structure of each chip set contacts that of the neighboring chip set. The heat sink and the substrate are disposed at two opposite sides of the chip sets, respectively. The circuit board is below the substrate. The solder balls are between the circuit board and the substrate.
Public/Granted literature
- US20100290193A1 Stacked-chip packaging structure and fabrication method thereof Public/Granted day:2010-11-18
Information query
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