Invention Grant
US08193845B2 Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise
有权
二进制加权的delta-sigma分数N频率合成器，具有数字到模拟微分器来消除量化噪声
- Patent Title: Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise
- Patent Title (中): 二进制加权的delta-sigma分数N频率合成器，具有数字到模拟微分器来消除量化噪声
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Application No.: US12831208Application Date: 2010-07-06
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Publication No.: US08193845B2Publication Date: 2012-06-05
- Inventor: Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
- Applicant: Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Incorporated
- Current Assignee: Microchip Technology Incorporated
- Current Assignee Address: US AZ Chandler
- Agency: King & Spalding L.L.P.
- Main IPC: H03L7/06
- IPC: H03L7/06
Abstract:
A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.
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