Invention Grant
- Patent Title: Selectable delay pulse generator
- Patent Title (中): 可选延迟脉冲发生器
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Application No.: US12510200Application Date: 2009-07-27
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Publication No.: US08193846B2Publication Date: 2012-06-05
- Inventor: John L. Fagan , Mark Bossard
- Applicant: John L. Fagan , Mark Bossard
- Applicant Address: US CA San Jose
- Assignee: Atmel Corporation
- Current Assignee: Atmel Corporation
- Current Assignee Address: US CA San Jose
- Agency: Fish & Richardson P.C.
- Main IPC: H03H11/26
- IPC: H03H11/26

Abstract:
A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.
Public/Granted literature
- US20090284296A1 SELECTABLE DELAY PULSE GENERATOR Public/Granted day:2009-11-19
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