Invention Grant
- Patent Title: Output circuit using analog amplifier
- Patent Title (中): 输出电路采用模拟放大器
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Application No.: US12662626Application Date: 2010-04-26
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Publication No.: US08193865B2Publication Date: 2012-06-05
- Inventor: Kouichi Nishimura
- Applicant: Kouichi Nishimura
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn Intellectual Property Law Group, PLLC
- Priority: JP2009-108338 20090427
- Main IPC: H03F1/52
- IPC: H03F1/52 ; H03F1/14

Abstract:
An output circuit includes an analog amplifier circuit including a differential amplifier stage configured to receive an input voltage, and first to nth output systems (n is a natural number more than 1); first to nth output nodes; an output pad; and first to nth electrostatic protection resistances. An ith output system (i is a natural number between 2 and n) of the first to nth output systems includes an ith PMOS transistor having a drain connected with the ith output node of the first to nth output nodes and a gate connected with a first output of the differential amplifier stage; and an ith NMOS transistor having a drain connected with the ith output node and a gate connected with a second output of the differential amplifier stage. The first to nth electrostatic protection resistances are respectively connected between the first to nth output nodes and the output pad.
Public/Granted literature
- US20100271129A1 Output circuit using analog amplifier Public/Granted day:2010-10-28
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