Invention Grant
US08194448B2 Technique to reduce FG-FG interference in multi bit NAND flash memory in case of adjacent pages not fully programmed
有权
在相邻页面未完全编程的情况下，减少多位NAND闪存中FG-FG干扰的技术
- Patent Title: Technique to reduce FG-FG interference in multi bit NAND flash memory in case of adjacent pages not fully programmed
- Patent Title (中): 在相邻页面未完全编程的情况下，减少多位NAND闪存中FG-FG干扰的技术
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Application No.: US12647317Application Date: 2009-12-24
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Publication No.: US08194448B2Publication Date: 2012-06-05
- Inventor: Violante Moschiano , Giovanni Santin
- Applicant: Violante Moschiano , Giovanni Santin
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Cool Patent, P.C.
- Agent Joseph P. Curtin
- Main IPC: G11C16/04
- IPC: G11C16/04
Abstract:
A method of reducing floating gate-floating gate interference in programming NAND flash memory is provided. Prior to programming an upper page of a memory cell, the method includes checking whether adjacent pages of near memory cells have been programmed. The method may program adjacent pages of near memory cells that have not been programmed.
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