Invention Grant
US08196026B2 Method and computer unit for error detection and logging in a memory
有权
用于错误检测和记录存储器的方法和计算机单元
- Patent Title: Method and computer unit for error detection and logging in a memory
- Patent Title (中): 用于错误检测和记录存储器的方法和计算机单元
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Application No.: US11887664Application Date: 2006-04-12
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Publication No.: US08196026B2Publication Date: 2012-06-05
- Inventor: Narayana Nagaraj
- Applicant: Narayana Nagaraj
- Applicant Address: DE Stuttgart
- Assignee: Robert Bosch GmbH
- Current Assignee: Robert Bosch GmbH
- Current Assignee Address: DE Stuttgart
- Agency: Kenyon & Kenyon LLP
- Priority: DE102005016801 20050412
- International Application: PCT/EP2006/061539 WO 20060412
- International Announcement: WO2006/108849 WO 20061019
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/00

Abstract:
In a method for detecting errors in computer data in a memory, a check sum is calculated in runtime and compared to a stored check sum. In this method, the computer data is being subdivided into at least two logical blocks and a check sum is calculated for each logical block. Also provided is a computer unit having a processor and a memory which has a ROM in which firmware is stored, and/or which has a RAM, the memory having at least two logging functions for logging established memory errors, e.g., errors in the ROM and/or the RAM.
Public/Granted literature
- US20090055718A1 Method and Computer Unit for Error Detection and Logging in a Memory Public/Granted day:2009-02-26
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