Invention Grant
- Patent Title: Signal routing and pin placement
- Patent Title (中): 信号路由和引脚放置
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Application No.: US12946106Application Date: 2010-11-15
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Publication No.: US08196082B1Publication Date: 2012-06-05
- Inventor: Parivallal Kannan
- Applicant: Parivallal Kannan
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent LeRoy D. Maunu; Lois D. Cartier
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
A method is provided for assigning signals to input pins of a component subject to asymmetric delays. A latency is determined for each signal-pin combination of the plurality of signals and plurality of input pins. The latency is determined as a function of an arrival time of the signal, a time to route the signal from to the input pin, and a time attributable to processing by the component. A latency threshold is selected. Signal to pin assignments using only signal-pin combinations having latencies less than or equal to the latency threshold are analyzed to determine if a one-to-one signal-to-pin assignment exists that includes all signals. The latency threshold is increased and the analysis is repeated until a valid one-to-one signal-to-pin assignment is found.
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