Invention Grant
- Patent Title: Stacked dual MOSFET package
- Patent Title (中): 堆叠双MOSFET封装
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Application No.: US12290309Application Date: 2008-10-29
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Publication No.: US08207017B2Publication Date: 2012-06-26
- Inventor: Sanjay Havanur
- Applicant: Sanjay Havanur
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Agency: Schein & Cai LLP
- Agent Jingming Cai
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/02

Abstract:
A method of fabricating a stacked dual MOSFET die package is disclosed. The method includes the steps of (a) forming a first conductive tab, (b) stacking a high side MOSFET die on the first conductive tab such that a drain contact of the high side MOSFET die is coupled to the first conductive tab, (c) stacking a second conductive tab in overlaying relationship to the high side MOSFET die such that a source contact of the high side MOSFET die is coupled to the second conductive tab, and (d) stacking a low side MOSFET die on the second conductive tab such that a drain contact of the low side MOSFET die is coupled to the second conductive tab.
Public/Granted literature
- US20090130799A1 Stacked dual MOSFET package Public/Granted day:2009-05-21
Information query
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