Invention Grant
- Patent Title: Semiconductor processing methods
- Patent Title (中): 半导体加工方法
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Application No.: US12720136Application Date: 2010-03-09
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Publication No.: US08207041B2Publication Date: 2012-06-26
- Inventor: Mark Kiehlbauch
- Applicant: Mark Kiehlbauch
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.
Public/Granted literature
- US20110221004A1 Semiconductor Constructions, And Semiconductor Processing Methods Public/Granted day:2011-09-15
Information query
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