Invention Grant
US08207060B2 High yield and high throughput method for the manufacture of integrated circuit devices of improved integrity, performance and reliability
有权
用于制造具有改进的完整性,性能和可靠性的集成电路器件的高产量和高产量方法
- Patent Title: High yield and high throughput method for the manufacture of integrated circuit devices of improved integrity, performance and reliability
- Patent Title (中): 用于制造具有改进的完整性,性能和可靠性的集成电路器件的高产量和高产量方法
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Application No.: US12339033Application Date: 2008-12-18
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Publication No.: US08207060B2Publication Date: 2012-06-26
- Inventor: Byung Chun Yang
- Applicant: Byung Chun Yang
- Agency: Haynes and Boone, LLP
- Agent Edward C. Kwok
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/302 ; H01L21/461

Abstract:
The present invention provides a method of forming a contact opening, such as a via hole, in which a sacrificial layer is deposited prior to exposing a conductor formed in a substrate at a bottom side of the opening to prevent damage and contamination to the materials constituting an integrated circuit device from happening. The exposing may or may not form a recess in the conductor. The present invention also provides a method of forming a contact opening having a recess in the conductor wherein a sacrificial layer is not deposited until the conductor is exposed, but deposited before a recess is formed in the conductor so that a major damage and contamination related to the recess formation can be prevented. By forming a trench feature over a contact opening formed by using the present invention, a dual damascene feature can be fabricated. By performing further damascene process steps over the various damascene interconnect features formed by using the present invention, various interconnect systems such as a single damascene planar via, a single damascene embedded via, and various dual damascene interconnect system having either a planar via or an embedded via can be fabricated.
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