Invention Grant
- Patent Title: Multilayer interconnection board
- Patent Title (中): 多层互连板
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Application No.: US12466604Application Date: 2009-05-15
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Publication No.: US08207452B2Publication Date: 2012-06-26
- Inventor: Issey Yamamoto , Akihiko Kamada
- Applicant: Issey Yamamoto , Akihiko Kamada
- Applicant Address: JP Kyoto
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Kyoto
- Agency: Keating & Bennett, LLP
- Priority: JP2006-340733 20061219
- Main IPC: H05K1/11
- IPC: H05K1/11

Abstract:
A multilayer interconnection board includes a plurality of laminated ceramic layers. Wiring electrodes are disposed on principal surfaces of the ceramic layers, and dot patterns are arranged around the wiring electrodes. The dot patterns are arranged such that the density distribution thereof is varied such that the ratio of the presence of the dot patterns in the vicinity of the wiring electrode is relatively large and the ratio of the presence is reduced as the distance from the wiring electrode increases.
Public/Granted literature
- US20090218123A1 MULTILAYER INTERCONNECTION BOARD Public/Granted day:2009-09-03
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