Invention Grant
- Patent Title: Semiconductor constructions
- Patent Title (中): 半导体结构
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Application No.: US12851896Application Date: 2010-08-06
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Publication No.: US08207570B2Publication Date: 2012-06-26
- Inventor: Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu
- Applicant: Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/788
- IPC: H01L29/788

Abstract:
Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.
Public/Granted literature
- US20100295114A1 Semiconductor Constructions Public/Granted day:2010-11-25
Information query
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