Invention Grant
- Patent Title: Semiconductor having a high aspect ratio via
- Patent Title (中): 具有高纵横比的半导体
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Application No.: US12898408Application Date: 2010-10-05
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Publication No.: US08207595B2Publication Date: 2012-06-26
- Inventor: Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
- Applicant: Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/40
- IPC: H01L29/40

Abstract:
A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.
Public/Granted literature
- US20120080761A1 SEMICONDUCTOR HAVING A HIGH ASPECT RATIO VIA Public/Granted day:2012-04-05
Information query
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