Invention Grant
- Patent Title: Electrical connections for multichip modules
- Patent Title (中): 多芯片模块的电气连接
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Application No.: US13154296Application Date: 2011-06-06
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Publication No.: US08207617B2Publication Date: 2012-06-26
- Inventor: Sunpil Youn , Seok-Chan Lee
- Applicant: Sunpil Youn , Seok-Chan Lee
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-wi, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-wi, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR2007-0073476 20070723
- Main IPC: H01L29/40
- IPC: H01L29/40
Abstract:
Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip pads connected to the conductive lines of the wafer. The wafer may then be protected with a packaging resin and singulated.
Public/Granted literature
- US20110285034A1 ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES Public/Granted day:2011-11-24
Information query
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