Invention Grant
- Patent Title: Ultra-low power multi-threshold asynchronous circuit design
- Patent Title (中): 超低功耗多阈值异步电路设计
-
Application No.: US13175168Application Date: 2011-07-01
-
Publication No.: US08207758B2Publication Date: 2012-06-26
- Inventor: Jia Di , Scott Christopher Smith
- Applicant: Jia Di , Scott Christopher Smith
- Applicant Address: US AR Little Rock
- Assignee: The Board of Trustees of the University of Arkansas
- Current Assignee: The Board of Trustees of the University of Arkansas
- Current Assignee Address: US AR Little Rock
- Agency: Michael Best & Friedrich LLP
- Main IPC: H03K19/20
- IPC: H03K19/20

Abstract:
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.
Public/Granted literature
- US20120133390A1 ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN Public/Granted day:2012-05-31
Information query
IPC分类: