A duty cycle correction circuit includes a duty adjustment circuit configured to generate an output clock by adjusting a duty cycle of an input clock in response to a duty adjustment code, a duty detection circuit configured to measure a difference between a width of a high pulse and a width of a low pulse of the output clock at each update period, and generate a duty detection code corresponding to the measured value, an accumulation circuit configured to generate the duty adjustment code by accumulating a value of the duty detection code outputted at each update period, and a toggling number adjustment circuit configured to adjust a toggling number of the output clock, which adjustment determines the update period, according to a frequency of the output clock.