Invention Grant
- Patent Title: Memory cell based array of tuning circuit
- Patent Title (中): 基于存储单元的调谐电路阵列
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Application No.: US12493239Application Date: 2009-06-28
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Publication No.: US08207802B2Publication Date: 2012-06-26
- Inventor: Hong-Yean Hsieh
- Applicant: Hong-Yean Hsieh
- Applicant Address: TW Science Park, Hsinchu
- Assignee: Realtek Semiconductor Corp.
- Current Assignee: Realtek Semiconductor Corp.
- Current Assignee Address: TW Science Park, Hsinchu
- Agency: IPR Works, LLC
- Main IPC: H03J3/20
- IPC: H03J3/20

Abstract:
A method applied in a tuning circuit comprising a plurality of turning cells is disclosed. the method comprises: laying out a array of tuning cells in a matrix configuration, the matrix comprising a first dimension and a second dimension; assigning a first index associated with the first dimension and a second index associated with the second dimension to each tuning cell; controlling each tuning cell using a word line and a bit line; and summing up outputs from all tuning cells to form a combined output. The tuning cell provides a first circuit value or a second circuit value according to the logical value of the bit line, and the difference between the first circuit value and the second circuit value is determined such that a turning resolution of the tuning circuit is determined.
Public/Granted literature
- US20100001818A1 MEMORY CELL BASED ARRAY OF TUNING CIRCUIT Public/Granted day:2010-01-07
Information query
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