Invention Grant
US08208279B2 Integrated circuit self aligned 3D memory array and manufacturing method
有权
集成电路自对准3D存储阵列及制造方法
- Patent Title: Integrated circuit self aligned 3D memory array and manufacturing method
- Patent Title (中): 集成电路自对准3D存储阵列及制造方法
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Application No.: US12692798Application Date: 2010-01-25
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Publication No.: US08208279B2Publication Date: 2012-06-26
- Inventor: Hang-Ting Lue
- Applicant: Hang-Ting Lue
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Kenta Suzue
- Main IPC: G11C5/06
- IPC: G11C5/06

Abstract:
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.
Public/Granted literature
- US20100226195A1 INTEGRATED CIRCUIT SELF ALIGNED 3D MEMORY ARRAY AND MANUFACTURING METHOD Public/Granted day:2010-09-09
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