A system LSI (100) having a logic circuit (104) and a plurality of SRAM macros (103) includes a power supply circuit (102) configured to receive a voltage (VDDP) supplied from the outside of the system LSI (100), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An SRAM memory cell (103a) of each of the plurality of SRAM macros (103) is supplied with the voltage (VDDM) generated by the power supply circuit (102), and an SRAM logic circuit (103b) of each of the plurality of SRAM macros (103) is supplied with a voltage (VDD) supplied from the outside. In addition, the logic circuit (104) is supplied with the voltage (VDD) from the outside.