Invention Grant
- Patent Title: Semiconductor memory device that can relief defective address
- Patent Title (中): 可以缓解缺陷地址的半导体存储器件
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Application No.: US12654202Application Date: 2009-12-14
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Publication No.: US08208324B2Publication Date: 2012-06-26
- Inventor: Noriaki Mochida , Kyoichi Nagata
- Applicant: Noriaki Mochida , Kyoichi Nagata
- Applicant Address: JP Chuo-ku, Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Chuo-ku, Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-317890 20081215
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C7/06 ; G11C8/00

Abstract:
To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized.
Public/Granted literature
- US20100149894A1 Semiconductor memory device that can relief defective address Public/Granted day:2010-06-17
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