A capacitance evaluation circuit includes a capacitive voltage divider, an analog-to-digital converter (ADC) and a processing module. The capacitive voltage divider includes a switch circuit, a known capacitor and a capacitor under test. The switch circuit is controlled by first and second clock signals. A voltage variation at a first terminal of the known capacitor is coupled to a first terminal of the capacitor under test based on a conduction state of the switch circuit. The ADC converts a voltage on the first terminal of the capacitor under test into a digital signal. The processing module detects a capacitance and a capacitance variation of the capacitor under test according to the digital signal from the ADC and a parameter of the ADC.