Invention Grant
US08209141B2 System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count
失效
用于自动生成用于集成电路设备的高速结构测试的测试模式的系统和方法,使用增量方法来减少测试图案计数
- Patent Title: System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count
- Patent Title (中): 用于自动生成用于集成电路设备的高速结构测试的测试模式的系统和方法,使用增量方法来减少测试图案计数
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Application No.: US12547637Application Date: 2009-08-26
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Publication No.: US08209141B2Publication Date: 2012-06-26
- Inventor: Robert W. Bassett , Andrew Ferko , Vikram Iyengar
- Applicant: Robert W. Bassett , Andrew Ferko , Vikram Iyengar
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb I.P. Law Firm, LLC
- Agent Michael J. LeStrange, Esq.
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G06F11/30

Abstract:
Disclosed are embodiments of a system and method for automatically selecting and generating test patterns for an at-speed structural test of an integrated circuit device. Specifically, a test pattern generation pass is started and proceeds until the “knee” of the simulated test coverage curve is observed. Next, the test patterns are optionally reordered and some are removed. Then, another test pattern generation pass is started. The process is repeated iteratively until some predetermined final stopping criterion is met. By performing multiple test pattern generation passes and reducing the number of available test patterns that can be generated with each pass, the method exploits the initial increase in the test coverage curve inherent in each pass and limits the overall test pattern count.
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