A system for a fast method to simulate phase lock loop (PLL) sub-block simulation is presented. The simulation of the sub-blocks of the PLL involve solving a system of non-linear equations for the voltages and currents in the sub-blocks of the PLL. A harmonic balance method is used to solve the system of non-linear equation. The harmonic balance method involves creating a system of linear equations which is solved using a novel hybrid time and frequency domain preconditioner. The hybrid time and frequency domain preconditioner includes the strong and fast convergence property of time-domain preconditioning while avoiding the potential divergent problems of time-domain preconditioning. In addition the hybrid time and frequency domain preconditioner also includes the dependable convergence of frequency domain preconditioning while avoiding the potential stalling problems of frequency domain preconditioning.