Invention Grant
US08209470B2 CPU data bus PLD/FPGA interface using dual port RAM structure built in PLD
失效
CPU数据总线PLD / FPGA接口使用双端口RAM结构内置PLD
- Patent Title: CPU data bus PLD/FPGA interface using dual port RAM structure built in PLD
- Patent Title (中): CPU数据总线PLD / FPGA接口使用双端口RAM结构内置PLD
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Application No.: US12421822Application Date: 2009-04-10
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Publication No.: US08209470B2Publication Date: 2012-06-26
- Inventor: Victor Mamontov
- Applicant: Victor Mamontov
- Applicant Address: US NJ Morristown
- Assignee: Honeywell International Inc.
- Current Assignee: Honeywell International Inc.
- Current Assignee Address: US NJ Morristown
- Agency: Shimokaji & Assoc., PC
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G11C8/00
Abstract:
A programmable logic device may include first and second ports in data communication with a memory block including a pair of address areas. A system using the programmable logic device may include the programmable logic device in data communication with a central processing unit and a controller. A method of using the programmable logic device may include generating a command from the central processing unit based on data read from one of the address areas and written to the second address area wherein the address areas are associated with a common memory address.
Public/Granted literature
- US20100262754A1 CPU DATA BUS PLD/FPGA INTERFACE USING DUAL PORT RAM STRUCTURE BUILT IN PLD Public/Granted day:2010-10-14
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