Invention Grant
- Patent Title: Memory system
- Patent Title (中): 内存系统
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Application No.: US12529192Application Date: 2009-02-10
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Publication No.: US08209471B2Publication Date: 2012-06-26
- Inventor: Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki
- Applicant: Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-051478 20080301
- International Application: PCT/JP2009/052598 WO 20090210
- International Announcement: WO2009/110304 WO 20090911
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.
Public/Granted literature
- US20110264859A1 MEMORY SYSTEM Public/Granted day:2011-10-27
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