Invention Grant
US08209503B1 Digital locked loop on channel tagged memory requests for memory optimization
有权
数字锁定环通道标记内存请求进行内存优化
- Patent Title: Digital locked loop on channel tagged memory requests for memory optimization
- Patent Title (中): 数字锁定环通道标记内存请求进行内存优化
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Application No.: US13196122Application Date: 2011-08-02
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Publication No.: US08209503B1Publication Date: 2012-06-26
- Inventor: Ronald D. Smith
- Applicant: Ronald D. Smith
- Applicant Address: BM
- Assignee: Marvell International Ltd.
- Current Assignee: Marvell International Ltd.
- Current Assignee Address: BM
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
A method and system for performing memory optimization is described. In one embodiment, a method includes receiving a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related requests of the read/write requests. Arrival times of the read/write requests assigned to each of the identifiers is measured and predicted arrival times of future read/write requests assigned to each of the identifiers is determined. A real-time schedule of memory requests is created using the arrival times of the read/write requests and the predicted arrival times. The method includes using the real-time schedule to determine idle periods and performing opportunistic functions in the memory during the idle periods, including performing at least one of garbage collection or translation cache pre-fetch.
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