Invention Grant
- Patent Title: Sequential element low power scan implementation
- Patent Title (中): 顺序元素低功耗扫描实现
-
Application No.: US12341825Application Date: 2008-12-22
-
Publication No.: US08209573B2Publication Date: 2012-06-26
- Inventor: Jeff S. Brown , Mark F. Turner , Jonathan Byrn
- Applicant: Jeff S. Brown , Mark F. Turner , Jonathan Byrn
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H03K3/289
Abstract:
A sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.
Public/Granted literature
- US20100162058A1 SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION Public/Granted day:2010-06-24
Information query
