Invention Grant
US08209639B2 Identifying layout regions susceptible to fabrication issues by using range patterns
有权
通过使用范围模式识别易受制造问题影响的布局区域
- Patent Title: Identifying layout regions susceptible to fabrication issues by using range patterns
- Patent Title (中): 通过使用范围模式识别易受制造问题影响的布局区域
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Application No.: US12362721Application Date: 2009-01-30
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Publication No.: US08209639B2Publication Date: 2012-06-26
- Inventor: Subarnarekha Sinha , Hailong Yao , Charles C. Chiang
- Applicant: Subarnarekha Sinha , Hailong Yao , Charles C. Chiang
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside the width range of a corresponding pattern slice then the layout block does not match the range pattern. If the comparison succeeds, further comparisons are made between a sequence of lengths of layout fragments in each layout slice and a sequence of length ranges of pattern fragments in corresponding pattern slices. If the length of any layout fragment falls outside the length range of a corresponding pattern fragment then the block does not match the range pattern. If all lengths are within their respective ranges, then the block matches the pattern, although additional constraints are checked in some embodiments.
Public/Granted literature
- US20090138835A1 IDENTIFYING LAYOUT REGIONS SUSCEPTIBLE TO FABRICATION ISSUES BY USING RANGE PATTERNS Public/Granted day:2009-05-28
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